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<div class="container" id="doc-container">
  <div class="edit"><a href="https://gem5.googlesource.com/public/gem5-website/+/refs/heads/master/README.md">Edit this page</a></div>
  <b>authors:</b> Andrew Bardsley<br>
  

  <br>
  <p>Minor CPU Model</p>

<p>This document contains a description of the structure and function of the
<a href="https://gem5.github.io/gem5-doxygen/namespaceMinor.html">Minor</a> gem5 in-order
processor model.</p>

<p>It is recommended reading for anyone who wants to understand
<a href="https://gem5.github.io/gem5-doxygen/namespaceMinor.html">Minor</a>’s internal
organisation, design decisions, C++ implementation and Python configuration. A
familiarity with gem5 and some of its internal structures is assumed. This
document is meant to be read alongside the
<a href="https://gem5.github.io/gem5-doxygen/namespaceMinor.html">Minor</a> source code
and to explain its general structure without being too slavish about naming
every function and data type.</p>

<h2 id="what-is-minor">What is Minor?</h2>

<p><a href="https://gem5.github.io/gem5-doxygen/namespaceMinor.html">Minor</a> is an in-order
processor model with a fixed pipeline but configurable data structures and
execute behaviour. It is intended to be used to model processors with strict
in-order execution behaviour and allows visualisation of an instruction’s
position in the pipeline through the MinorTrace/minorview.py format/tool. The
intention is to provide a framework for micro-architecturally correlating the
model with a particular, chosen processor with similar capabilities.</p>

<h2 id="design-philosophy">Design Philosophy</h2>

<h3 id="multithreading">Multithreading</h3>

<p>The model isn’t currently capable of multithreading but there are THREAD
comments in key places where stage data needs to be arrayed to support
multithreading.</p>

<h3 id="data-structures">Data structures</h3>

<p>Decorating data structures with large amounts of life-cycle information is
avoided. Only instructions
(<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html">MinorDynInst</a>) contain a
significant proportion of their data content whose values are not set at
construction.</p>

<p>All internal structures have fixed sizes on construction. Data held in queues
and FIFOs (<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorBuffer.html">MinorBuffer</a>,
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1FUPipeline.html">FUPipeline</a>) should have
a <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1BubbleIF.html">BubbleIF</a>
interface to allow a distinct ‘bubble’/no data value option for each type.</p>

<p>Inter-stage ‘struct’ data is packaged in structures which are passed by value.
Only <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html">MinorDynInst</a>, the line
data in <a href="https://gem5.github.io/gem5-doxygen/classMinorCPU.html#a36a7ec6a8c5a6d27fd013d8b0238029d">ForwardLineData</a>
and the memory-interfacing objects <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1_1_1FetchRequest.html">Fetch1::FetchRequest</a>
and <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ_1_1LSQRequest.html">LSQ::LSQRequest</a> are
<code class="highlighter-rouge">::new</code> allocated while running the model.</p>

<h2 id="model-structure">Model structure</h2>

<p>Objects of class <a href="https://gem5.github.io/gem5-doxygen/classMinorCPU.html">MinorCPU</a> are provided by the
model to gem5. <a href="https://gem5.github.io/gem5-doxygen/classMinorCPU.html">MinorCPU</a> implements the
interfaces of (cpu.hh) and can provide data and instruction interfaces for
connection to a cache system. The model is configured in a similar way to other
gem5 models through Python. That configuration is passed on to
<a href="https://gem5.github.io/gem5-doxygen/classMinorCPU.html#a36a7ec6a8c5a6d27fd013d8b0238029d">MinorCPU::pipeline</a>
(of class <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Pipeline.html">Pipeline</a>) which
actually implements the processor pipeline.</p>

<p>The hierarchy of major unit ownership from <a href="https://gem5.github.io/gem5-doxygen/classMinorCPU.html">MinorCPU</a> down looks like this:</p>

<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="p">MinorCPU
</span><span class="gd">--- Pipeline - container for the pipeline, owns the cyclic 'tick' event mechanism and the idling (cycle skipping) mechanism.
--- --- Fetch1 - instruction fetch unit responsible for fetching cache lines (or parts of lines from the I-cache interface).
--- --- --- Fetch1::IcachePort - interface to the I-cache from Fetch1.
--- --- Fetch2 - line to instruction decomposition.
--- --- Decode - instruction to micro-op decomposition.
--- --- Execute - instruction execution and data memory interface.
--- --- --- LSQ - load store queue for memory ref. instructions.
--- --- --- LSQ::DcachePort - interface to the D-ache from Execute.
</span></code></pre></div></div>

<h2 id="key-data-structures">Key data structures</h2>

<h3 id="instruction-and-line-identity-instld-dyn_insthh">Instruction and line identity: Instld (<code class="highlighter-rouge">dyn_inst.hh</code>)</h3>

<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code>- T/S.P/L - for fetched cache lines
- T/S.P/L/F - for instructions before Decode
- T/S.P/L/F.E - for instructions from Decode onwards
</code></pre></div></div>

<p>for example:</p>

<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code>- 0/10.12/5/6.7
</code></pre></div></div>

<p><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1InstId.html">InstId</a> fields
are:</p>

<table>
  <thead>
    <tr>
      <th style="text-align: left">Field</th>
      <th style="text-align: left">Symbol</th>
      <th style="text-align: left">Generated by</th>
      <th style="text-align: left">Checked by</th>
      <th style="text-align: left">Function</th>
    </tr>
  </thead>
  <tbody>
    <tr>
      <td style="text-align: left">InstId::threadId</td>
      <td style="text-align: left">T</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a></td>
      <td style="text-align: left">Everywhere the thread number is needed</td>
      <td style="text-align: left">Thread number (currently always 0).</td>
    </tr>
    <tr>
      <td style="text-align: left">InstId::streamSeqNum</td>
      <td style="text-align: left">S</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a></td>
      <td style="text-align: left">Fetch1, Fetch2, Execute (to discard lines/insts)</td>
      <td style="text-align: left">Stream sequence number as chosen by Execute. Stream sequence numbers change after changes of PC (branches, exceptions) in Execue and are used to separate pre and post brnach instrucion streams.</td>
    </tr>
    <tr>
      <td style="text-align: left">InstId::predictionSeqNum</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html">Fetch2</a></td>
      <td style="text-align: left">Fetch2 (while discarding lines after prediction)</td>
      <td style="text-align: left">Prediction sequence numbers represent branch prediction decisions. This is used by Fetch2 to mark lines/instructions/ according to the last followed branch prediction made by Fetch2. Fetch2 can signal to Fetch1 that it should change its fetch address and mark lines with a new prediction sequence number (which it will only do if the stream sequence number Fetch1 expects matches that of the request).</td>
      <td style="text-align: left"> </td>
    </tr>
    <tr>
      <td style="text-align: left">InstId::lineSeqNum</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a></td>
      <td style="text-align: left">(just for debugging)</td>
      <td style="text-align: left">Line fetch sequence number of this cache line or the line this instruction was extracted from.</td>
      <td style="text-align: left"> </td>
    </tr>
    <tr>
      <td style="text-align: left">InstId::fetchSeqNum</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html">Fetch2</a></td>
      <td style="text-align: left">Fetch2 (as the inst. sequence number for branches)</td>
      <td style="text-align: left">Instruction fetch order assigned by Fetch2 when lines are decomposed into instructions.</td>
      <td style="text-align: left"> </td>
    </tr>
    <tr>
      <td style="text-align: left">InstId::execSeqNum</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html">Decode</a></td>
      <td style="text-align: left">Execute (to check instruction identify in queues/FUs/LSQ</td>
      <td style="text-align: left">Instruction order after micro-op decomposition</td>
      <td style="text-align: left"> </td>
    </tr>
  </tbody>
</table>

<p>The sequence number fields are all independent of each other and although, for
instance, <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1InstId.html#a064b0e4480268559e68510311be2a9b0">InstId::execSeqNum</a>
for an instruction will always be &gt;= <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1InstId.html#a06677e68051a2a52f384e55e9368e33d">InstId::fetchSeqNum</a>,
the comparison is not useful.</p>

<p>The originating stage of each sequence number field keeps a counter for that
field which can be incremented in order to generate new, unique numbers.</p>

<h3 id="instructi-ns-minordyninst-dyn_insthh">Instructi ns: MinorDynInst (<code class="highlighter-rouge">dyn_inst.hh</code>)</h3>

<p><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html">MinorDynInst</a> represents
an instruction’s progression through the pipeline. An instruction can be three
things:</p>

<table>
  <thead>
    <tr>
      <th style="text-align: left">Things</th>
      <th style="text-align: left">Predicate</th>
      <th style="text-align: left">Explanation</th>
    </tr>
  </thead>
  <tbody>
    <tr>
      <td style="text-align: left">A bubble</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#a24e835fa495026ca63ffec43ee9cc07e">MinorDynInst::isBubble()</a></td>
      <td style="text-align: left">no instruction at all, just a space-filler</td>
    </tr>
    <tr>
      <td style="text-align: left">A fault</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#a24029f3cd1835928d572737a548a824e">MinorDynInst::isFault()</a></td>
      <td style="text-align: left">a fault to pass down the pipeline in an insturction’s clothing</td>
    </tr>
    <tr>
      <td style="text-align: left">A decoded instruction</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#adc55cdcf9f7c6588bb27eddb4c7fe38e">MinorDynInst::isInst()</a></td>
      <td style="text-align: left">instructions are actually passed to the gem5 decoder in Fetch2 and so are created fully decoded. MinorDynInst::staticInst is the decoded instruction form.</td>
    </tr>
  </tbody>
</table>

<p>Instructions are reference counted using the gem5 <a href="https://gem5.github.io/gem5-doxygen/classRefCountingPtr.html">RefCountingPtr</a> 
(<a href="https://gem5.github.io/gem5-doxygen/refcnt_8hh.html">base/refcnt.hh</a>)
wrapper. They therefore usually appear as MinorDynInstPtr in code. Note that as
<a href="https://gem5.github.io/gem5-doxygen/classRefCountingPtr.html">RefCountingPtr</a>
initialises as nullptr rather than an object that supports
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1BubbleIF.html#a7ce121301dba2e89b94235d96bf339ae">BubbleIF::isBubble</a>
passing raw MinorDynInstPtrs to <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Queue.html">Queues</a> and other similar
structures from stage.hh without boxing is dangerous.</p>

<h3 id="forwardlinedata-pipe_datahh">ForwardLineData (<code class="highlighter-rouge">pipe_data.hh</code>)</h3>

<p>ForwardLineData is used to pass cache lines from Fetch1 to Fetch2. Like
MinorDynInsts, they can be bubbles (<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1ForwardLineData.html#a46789690719acf167be0a57c9d7d4f8f">ForwardLineData::isBubble()</a>),
fault-carrying or can contain a line (partial line) fetched by Fetch1. The data
carried by ForwardLineData is owned by a Packet object returned from memory and
is explicitly memory managed and do must be deleted once processed (by Fetch2
deleting the Packet).</p>

<h3 id="forwardinstdata-pipe_datahh">ForwardInstData (<code class="highlighter-rouge">pipe_data.hh</code>)</h3>

<p>ForwardInstData can contain up to <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1ForwardInstData.html#ad5db21f655f2f1dfff69e6f6d5cc606e">ForwardInstData::width()</a>
instructions in its <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1ForwardInstData.html#ab54a61c683376aaf5a12ea19ab758340">ForwardInstData::insts</a>
vector. This structure is used to carry instructions between Fetch2, Decode and
Execute and to store input buffer vectors in Decode and Execute.</p>

<h3 id="fetch1fetchrequest-fetch1hh">Fetch1::FetchRequest (<code class="highlighter-rouge">fetch1.hh</code>)</h3>

<p>FetchRequests represent I-cache line fetch requests. The are used in the memory
queues of Fetch1 and are pushed into/popped from <a href="https://gem5.github.io/gem5-doxygen/classPacket.html#ad1dd4fa4370e508806fe4a8253a0ad12">Packet::senderState</a>
while traversing the memory system.</p>

<p>FetchRequests contain a memory system Request (<a href="https://gem5.github.io/gem5-doxygen/request_8hh.html">mem/request.hh</a>) for that fetch access, a
packet (Packet, <a href="https://gem5.github.io/gem5-doxygen/packet_8hh.html">mem/packet.hh</a>), if the request gets to
memory, and a fault field that can be populated with a TLB-sourced prefetch
fault (if any).</p>

<h3 id="lsqlsqrequest-executehh">LSQ::LSQRequest (<code class="highlighter-rouge">execute.hh</code>)</h3>

<p>LSQRequests are similar to FetchRequests but for D-cache accesses. They carry
the instruction associated with a memory access.</p>

<h2 id="the-pipeline">The pipeline</h2>

<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="gd">------------------------------------------------------------------------------
</span>    Key:

    [] : inter-stage BufferBuffer
    ,--.
    |  | : pipeline stage
    `--'
    ---&gt; : forward communication
    &lt;--- : backward communication

    rv : reservation information for input buffers

                ,------.     ,------.     ,------.     ,-------.
 (from  --[]-v-&gt;|Fetch1|-[]-&gt;|Fetch2|-[]-&gt;|Decode|-[]-&gt;|Execute|--&gt; (to Fetch1
 Execute)    |  |      |&lt;-[]-|      |&lt;-rv-|      |&lt;-rv-|       |     &amp; Fetch2)
             |  `------'&lt;-rv-|      |     |      |     |       |
             `--------------&gt;|      |     |      |     |       |
                             `------'     `------'     `-------'
<span class="gd">------------------------------------------------------------------------------
</span></code></pre></div></div>

<p>The four pipeline stages are connected together by <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorBuffer.html">MinorBuffer</a> FIFO
(stage.hh, derived ultimately from <a href="https://gem5.github.io/gem5-doxygen/classTimeBuffer.html">TimeBuffer</a>) structures which
allow inter-stage delays to be modelled. There is a <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorBuffer.html">MinorBuffers</a> between
adjacent stages in the forward direction (for example: passing lines from
Fetch1 to Fetch2) and, between Fetch2 and Fetch1, a buffer in the backwards
direction carrying branch predictions.</p>

<p>Stages Fetch2, Decode and Execute have input buffers which, each cycle, can
accept input data from the previous stage and can hold that data if the stage
is not ready to process it. Input buffers store data in the same form as it is
received and so Decode and Execute’s input buffers contain the output
instruction vector (<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1ForwardInstData.html">ForwardInstData</a>
(<a href="https://gem5.github.io/gem5-doxygen/pipe__data_8hh.html">pipe_data.hh</a>)) from
their previous stages with the instructions and bubbles in the same positions
as a single buffer entry.</p>

<p>Stage input buffers provide a <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Reservable.html">Reservable</a> (stage.hh)
interface to their previous stages, to allow slots to be reserved in their
input buffers, and communicate their input buffer occupancy backwards to allow
the previous stage to plan whether it should make an output in a given cycle.</p>

<h3 id="event-handling-minoractivityrecorder-activityhh-pipelinehh">Event handling: MinorActivityRecorder (<code class="highlighter-rouge">activity.hh</code>, <code class="highlighter-rouge">pipeline.hh</code>)</h3>

<p>Minor is essentially a cycle-callable model with some ability to skip cycles
based on pipeline activity. External events are mostly received by callbacks
(e.g. <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1_1_1IcachePort.html#aec62b3d89dfe61e8528cdcdf3729eeab">Fetch1::IcachePort::recvTimingResp</a>)
and cause the pipeline to be woken up to service advancing request queues.</p>

<p><a href="https://gem5.github.io/gem5-doxygen/classTicked.html">Ticked</a> (sim/ticked.hh)
is a base class bringing together an evaluate member function and a provided
<a href="https://gem5.github.io/gem5-doxygen/classSimObject.html">SimObject</a>. It
provides a <a href="https://gem5.github.io/gem5-doxygen/classTicked.html#a798d1e248c27161de6eb2bc6fef5e425">Ticked::start</a>/stop
interface to start and pause clock events from being periodically issued.
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Pipeline.html">Pipeline</a> is
a derived class of Ticked.</p>

<p>During evaluate calls, stages can signal that they still have work to do in the
next cycle by calling either <a href="https://gem5.github.io/gem5-doxygen/classMinorCPU.html#ae3b03c96ee234e2c5c6c68f4567245a7">MinorCPU::activityRecorder</a>-&gt;activity()
(for non-callable related activity) or MinorCPU::wakeupOnEvent(<stageId>) (for
stage callback-related 'wakeup' activity).</stageId></p>

<p><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Pipeline.html#af07fdce00c8937e9de5b6450a1cd62bf">Pipeline::evaluate</a>
contains calls to evaluate for each unit and a test for pipeline idling which
can turns off the clock tick if no unit has signalled that it may become active
next cycle.</p>

<p>Within Pipeline (<a href="https://gem5.github.io/gem5-doxygen/pipeline_8hh.html">pipeline.hh</a>), the stages are
evaluated in reverse order (and so will ::evaluate in reverse order) and their
backwards data can be read immediately after being written in each cycle
allowing output decisions to be ‘perfect’ (allowing synchronous stalling of the
whole pipeline). Branch predictions from Fetch2 to Fetch1 can also be
transported in 0 cycles making fetch1ToFetch2BackwardDelay the only
configurable delay which can be set as low as 0 cycles.</p>

<p>The <a href="https://gem5.github.io/gem5-doxygen/classMinorCPU.html#a854596342bfb9dd889437e494c4ddb27">MinorCPU::activateContext</a>
and <a href="https://gem5.github.io/gem5-doxygen/classMinorCPU.html#ae6aa9b1bb798d8938f0b35e11d9e68b8">MinorCPU::suspendContext</a>
interface can be called to start and pause threads (threads in the MT sense)
and to start and pause the pipeline. Executing instructions can call this
interface (indirectly through the ThreadContext) to idle the CPU/their threads.</p>

<h3 id="each-pipeline-stage">Each pipeline stage</h3>

<p>In general, the behaviour of a stage (each cycle) is:</p>

<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code>    evaluate:
        push input to inputBuffer
        setup references to input/output data slots

        do 'every cycle' 'step' tasks

        if there is input and there is space in the next stage:
            process and generate a new output
            maybe re-activate the stage

        send backwards data

        if the stage generated output to the following FIFO:
            signal pipe activity

        if the stage has more processable input and space in the next stage:
            re-activate the stage for the next cycle

        commit the push to the inputBuffer if that data hasn't all been used
</code></pre></div></div>

<p>The Execute stage differs from this model as its forward output (branch) data
is unconditionally sent to Fetch1 and Fetch2. To allow this behaviour, Fetch1
and Fetch2 must be unconditionally receptive to that data.</p>

<h3 id="fetch1-stage">Fetch1 stage</h3>

<p><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a> is
responsible for fetching cache lines or partial cache lines from the I-cache
and passing them on to <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html">Fetch2</a> to be decomposed
into instructions. It can receive ‘change of stream’ indications from both
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a> and
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html">Fetch2</a> to
signal that it should change its internal fetch address and tag newly fetched
lines with new stream or prediction sequence numbers. When both Execute and
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html">Fetch2</a> signal
changes of stream at the same time, <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a> takes
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a>’s
change.</p>

<p>Every line issued by <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a> will bear a
unique line sequence number which can be used for debugging stream changes.</p>

<p>When fetching from the I-cache, <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a>  will ask for
data from the current fetch address (Fetch1::pc) up to the end of the ‘data
snap’ size set in the parameter fetch1LineSnapWidth. Subsequent autonomous line
fetches will fetch whole lines at a snap boundary and of size fetch1LineWidth.</p>

<p><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a> will
only initiate a memory fetch if it can reserve space in <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html">Fetch2</a> input buffer.
That input buffer serves an the fetch queue/LFL for the system.</p>

<p><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a>
contains two queues: requests and transfers to handle the stages of translating
the address of a line fetch (via the TLB) and accommodating the
request/response of fetches to/from memory.</p>

<p>Fetch requests from <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a> are pushed into
the requests queue as newly allocated FetchRequest objects once they have been
sent to the ITLB with a call to itb-&gt;translateTiming.</p>

<p>A response from the TLB moves the request from the requests queue to the
transfers queue. If there is more than one entry in each queue, it is possible
to get a TLB response for request which is not at the head of the requests
queue. In that case, the TLB response is marked up as a state change to
Translated in the request object, and advancing the request to transfers (and
the memory system) is left to calls to <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html#ac143710b93ec9f55bfc3e2882ef2fe4c">Fetch1::stepQueues</a>
which is called in the cycle following any event is received.</p>

<p><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html#a9ace21e8131caf360190ea876cfa2934">Fetch1::tryToSendToTransfers</a>
—
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title: Execution Basics
doc: gem5 documentation
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permalink: /documentation/general_docs/cpu_models/execution_basics
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<p>is responsible for moving requests between the two queues and issuing requests
to memory. Failed TLB lookups (prefetch aborts) continue to occupy space in the
queues until they are recovered at the head of transfers.</p>

<p>Responses from memory change the request object state to Complete and
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html#a68a0a88ce6ee3dd170c977318cfb4ca9">Fetch1::evaluate</a>
can pick up response data, package it in the <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1ForwardLineData.html">ForwardLineData</a> object,
and forward it to <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html">Fetch2</a>’s input buffer.</p>

<p>As space is always reserved in <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html#afdaa27275e2f605d9aaa637e8c39f96d">Fetch2::inputBuffer</a>,
setting the input buffer’s size to 1 results in non-prefetching behaviour.</p>

<p>When a change of stream occurs, translated requests queue members and completed
transfers queue members can be unconditionally discarded to make way for new
transfers.</p>

<h3 id="fetch2-stage">Fetch2 stage</h3>

<p>Fetch2 receives a line from Fetch1 into its input buffer. The data in the head
line in that buffer is iterated over and separated into individual instructions
which are packed into a vector of instructions which can be passed to
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html">Decode</a>.
Packing instructions can be aborted early if a fault is found in either the
input line as a whole or a decomposed instruction.</p>

<h4 id="branch-prediction">Branch prediction</h4>

<p>Fetch2 contains the branch prediction mechanism. This is a wrapper around the branch predictor interface provided by gem5 (cpu/pred/…).</p>

<p>Branches are predicted for any control instructions found. If prediction is
attempted for an instruction, the <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#a905b0516019ae7f47b5795ceda33f5cd">MinorDynInst::triedToPredict</a>
flag is set on that instruction.</p>

<p>When a branch is predicted to take, the <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#aa57659ef9d30162ddcf10fcb0f3963ac">MinorDynInst::predictedTaken</a> flag is set and <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#a5eaf9547bcaefa2c0fd37f32c828691b">MinorDynInst::predictedTarget</a> is set to the predicted target PC value. The predicted branch instruction is then packed into Fetch2’s output vector, the prediction sequence number is incremented, and the branch is communicated to Fetch1.</p>

<p>After signalling a prediction, Fetch2 will discard its input buffer contents
and will reject any new lines which have the same stream sequence number as
that branch but have a different prediction sequence number. This allows
following sequentially fetched lines to be rejected without ignoring new lines
generated by a change of stream indicated from a ‘real’ branch from Execute
(which will have a new stream sequence number).</p>

<p>The program counter value provided to Fetch2 by Fetch1 packets is only updated
when there is a change of stream. Fetch2::havePC indicates whether the PC will
be picked up from the next processed input line. Fetch2::havePC is necessary to
allow line-wrapping instructions to be tracked through decode.</p>

<p>Branches (and instructions predicted to branch) which are processed by Execute
will generate BranchData (<a href="https://gem5.github.io/gem5-doxygen/pipe__data_8hh.html">pipe_data.hh</a>) data explaining the
outcome of the branch which is sent forwards to Fetch1 and Fetch2. Fetch1 uses
this data to change stream (and update its stream sequence number and address
for new lines). Fetch2 uses it to update the branch predictor. Minor does not
communicate branch data to the branch predictor for instructions which are
discarded on the way to commit.</p>

<p>BranchData::BranchReason (<a href="https://gem5.github.io/gem5-doxygen/pipe__data_8hh.html">pipe_data.hh</a>) encodes the possible
branch scenarios:</p>

<table>
  <thead>
    <tr>
      <th style="text-align: left">Branch enum val.</th>
      <th style="text-align: left">In Execute</th>
      <th style="text-align: left">Fetch1 reaction</th>
      <th style="text-align: left">Fetch2 reaction</th>
    </tr>
  </thead>
  <tbody>
    <tr>
      <td style="text-align: left">No Branch</td>
      <td style="text-align: left">(output bubble data)</td>
      <td style="text-align: left">-</td>
      <td style="text-align: left">-</td>
    </tr>
    <tr>
      <td style="text-align: left">CorrectlyPredictedBranch</td>
      <td style="text-align: left">Predicted, taken</td>
      <td style="text-align: left">-</td>
      <td style="text-align: left">Update BP as taken branch</td>
    </tr>
    <tr>
      <td style="text-align: left">UnpredictedBranch</td>
      <td style="text-align: left">Not predicted, taken and was taken</td>
      <td style="text-align: left">New stream</td>
      <td style="text-align: left">Update BP as taken branch</td>
    </tr>
    <tr>
      <td style="text-align: left">BadlyPredictedBranch</td>
      <td style="text-align: left">Predicted, not taken</td>
      <td style="text-align: left">New stream to restore to old Inst. source</td>
      <td style="text-align: left">Update BP as not taken branch</td>
    </tr>
    <tr>
      <td style="text-align: left">BadlyPredictedBranchTarget</td>
      <td style="text-align: left">Predicted, taken, but to a different target than predicted one</td>
      <td style="text-align: left">New stream</td>
      <td style="text-align: left">Update BTB to new target</td>
    </tr>
    <tr>
      <td style="text-align: left">SuspendThread</td>
      <td style="text-align: left">Hint to suspend fetch</td>
      <td style="text-align: left">Suspend fetch for this thread (branch to next inst. as wakeup fetch addr</td>
      <td style="text-align: left">-</td>
    </tr>
    <tr>
      <td style="text-align: left">Interrupt</td>
      <td style="text-align: left">Interrupt detected</td>
      <td style="text-align: left">New stream</td>
      <td style="text-align: left">-</td>
    </tr>
  </tbody>
</table>

<hr />
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<h3 id="decode-stage">Decode Stage</h3>

<p><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html">Decode</a> takes a
vector of instructions from <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html">Fetch2</a> (via its input
buffer) and decomposes those instructions into micro-ops (if necessary) and
packs them into its output instruction vector.</p>

<p>The parameter executeInputWidth sets the number of instructions which can be
packed into the output per cycle. If the parameter decodeCycleInput is true,
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html">Decode</a> can try
to take instructions from more than one entry in its input buffer per cycle.</p>

<h3 id="execute-stage">Execute Stage</h3>

<p>Execute provides all the instruction execution and memory access mechanisms. An
instructions passage through Execute can take multiple cycles with its precise
timing modelled by a functional unit pipeline FIFO.</p>

<p>A vector of instructions (possibly including fault ‘instructions’) is provided
to Execute by Decode and can be queued in the Execute input buffer before being
issued. Setting the parameter executeCycleInput allows execute to examine more
than one input buffer entry (more than one instruction vector). The number of
instructions in the input vector can be set with executeInputWidth and the
depth of the input buffer can be set with parameter executeInputBufferSize.</p>

<h4 id="functional-units">Functional units</h4>

<p>The Execute stage contains pipelines for each functional unit comprising the
computational core of the CPU. Functional units are configured via the
executeFuncUnits parameter. Each functional unit has a number of instruction
classes it supports, a stated delay between instruction issues, and a delay
from instruction issue to (possible) commit and an optional timing annotation
capable of more complicated timing.</p>

<p>Each active cycle, <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#a2d6ca9a694bf99ef82da7759cba8c3da">Execute::evaluate</a>
performs this action:</p>

<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code>    Execute::evaluate:
        push input to inputBuffer
        setup references to input/output data slots and branch output slot

        step D-cache interface queues (similar to Fetch1)

        if interrupt posted:
            take interrupt (signalling branch to Fetch1/Fetch2)
        else
            commit instructions
            issue new instructions

        advance functional unit pipelines

        reactivate Execute if the unit is still active

        commit the push to the inputBuffer if that data hasn't all been used
</code></pre></div></div>

<h4 id="functional-unit-fifos">Functional unit FIFOs</h4>

<p>Functional units are implemented as SelfStallingPipelines (stage.hh). These are
<a href="https://gem5.github.io/gem5-doxygen/classTimeBuffer.html">TimeBuffer</a> FIFOs
with two distinct ‘push’ and ‘pop’ wires. They respond to
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1SelfStallingPipeline.html#ad933640bc6aab559c009302e478c3768">SelfStallingPipeline::advance</a>
in the same way as TimeBuffers unless there is data at the far, ‘pop’, end of
the FIFO. A ‘stalled’ flag is provided for signalling stalling and to allow a
stall to be cleared. The intention is to provide a pipeline for each functional
unit which will never advance an instruction out of that pipeline until it has
been processed and the pipeline is explicitly unstalled.</p>

<p>The actions ‘issue’, ‘commit’, and ‘advance’ act on the functional units.</p>

<h4 id="issue">Issue</h4>

<p>Issuing instructions involves iterating over both the input buffer instructions
and the heads of the functional units to try and issue instructions in order.
The number of instructions which can be issued each cycle is limited by the
parameter executeIssueLimit, how executeCycleInput is set, the availability of
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<p>pipeline space and the policy used to choose a pipeline in which the
instruction can be issued.</p>

<p>At present, the only issue policy is strict round-robin visiting of each
pipeline with the given instructions in sequence. For greater flexibility,
better (and more specific policies) will need to be possible.</p>

<p>Memory operation instructions traverse their functional units to perform their
EA calculations. On ‘commit’, the <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1ExecContext.html">ExecContext</a>::initiateAcc
execution phase is performed and any memory access is issued (via.
ExecContext::{read,write}Mem calling <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ.html#a18594a4baa4eef7bfc3be45c03f4d544">LSQ::pushRequest</a>)
to the <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ.html">LSQ</a>.</p>

<p>Note that faults are issued as if they are instructions and can (currently) be
issued to any functional unit.</p>

<p>Every issued instruction is also pushed into the Execute::inFlightInsts queue.
Memory ref. instructions are pushing into Execute::inFUMemInsts queue.</p>

<h4 id="commit">Commit</h4>

<p>Instructions are committed by examining the head of the Execute::inFlightInsts
queue (which is decorated with the functional unit number to which the
instruction was issued). Instructions which can then be found in their
functional units are executed and popped from Execute::inFlightInsts.</p>

<p>Memory operation instructions are committed into the memory queues (as
described above) and exit their functional unit pipeline but are not popped
from the Execute::inFlightInsts queue. The Execute::inFUMemInsts queue provides
ordering to memory operations as they pass through the functional units
(maintaining issue order). On entering the LSQ, instructions are popped from
Execute::inFUMemInsts.</p>

<p>If the parameter executeAllowEarlyMemoryIssue is set, memory operations can be
sent from their FU to the LSQ before reaching the head of
Execute::inFlightInsts but after their dependencies are met.
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#ac72a9dcff570bbaf24da9ee74392e6d0">MinorDynInst::instToWaitFor</a>
is marked up with the latest dependent instruction execSeqNum required to be
committed for a memory operation to progress to the LSQ.</p>

<p>Once a memory response is available (by testing the head of
Execute::inFlightInsts against <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ.html#a458abe5d220a0f66600bf339bceb2100">LSQ::findResponse</a>),
commit will process that response (ExecContext::completeAcc) and pop the
instruction from Execute::inFlightInsts.</p>

<p>Any branch, fault or interrupt will cause a stream sequence number change and
signal a branch to Fetch1/Fetch2. Only instructions with the current stream
sequence number will be issued and/or committed.</p>

<h4 id="advance">Advance</h4>

<p>All non-stalled pipeline are advanced and may, thereafter, become stalled.
Potential activity in the next cycle is signalled if there are any instructions
remaining in any pipeline.</p>

<h4 id="scoreboard">Scoreboard</h4>

<p>The scoreboard (<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Scoreboard.html">Scoreboard</a>) is used to
control instruction issue. It contains a count of the number of in flight
instructions which will write each general purpose CPU integer or float
register. Instructions will only be issued where the scoreboard contains a
count of 0 instructions which will write to one of the instructions source
registers.</p>

<p>Once an instruction is issued, the scoreboard counts for each destination
register for an instruction will be incremented.</p>

<p>The estimated delivery time of the instruction’s result is marked up in the scoreboard by adding the length of the issued-to FU to the current time. The timings parameter on each FU provides a list of additional rules for calculating the delivery time. These are documented in the parameter comments in MinorCPU.py.</p>

<p>On commit, (for memory operations, memory response commit) the scoreboard counters for an instruction’s source registers are decremented. will be decremented.</p>

<h4 id="executeinflightinsts">Execute::inFlightInsts</h4>

<p>The Execute::inFlightInsts queue will always contain all instructions in flight
in <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a> in
the correct issue order. <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#af0b90170a273f1a0d41f4164ba3fe456">Execute::issue</a>
is the only process which will push an instruction into the queue.
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#ac2da0ae4202602ce4ad976f33a004237">Execute::commit</a>
is the only process that can pop an instruction.</p>

<h4 id="lsq">LSQ</h4>

<p>The <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ.html">LSQ</a> can
support multiple outstanding transactions to memory in a number of conservative
cases.</p>

<p>There are three queues to contain requests: requests, transfers and the store
buffer. The requests and transfers queue operate in a similar manner to the
queues in Fetch1. The store buffer is used to decouple the delay of completing
store operations from following loads.</p>

<p>Requests are issued to the DTLB as their instructions leave their functional
unit. At the head of requests, cacheable load requests can be sent to memory
and on to the transfers queue. Cacheable stores will be passed to transfers
unprocessed and progress that queue maintaining order with other transactions.</p>

<p>The conditions in <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ.html#a7d7b8ddc7c69fd9eb3b8594fe261d8e8">LSQ::tryToSendToTransfers</a>
dictate when requests can be sent to memory.</p>

<p>All uncacheable transactions, split transactions and locked transactions are
processed in order at the head of requests. Additionally, store results
residing in the store buffer can have their data forwarded to cacheable loads
(removing the need to perform a read from memory) but no cacheable load can be
issue to the transfers queue until that queue’s stores have drained into the
store buffer.</p>

<p>At the end of transfers, requests which are <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ_1_1LSQRequest.html#a429d50f5dd6be4217d5dba93f8c289d3a81b9dbf6670e396d0266949d59b57428">LSQ::LSQRequest::Complete</a>
(are faulting, are cacheable stores, or have been sent to memory and received a
response) can be picked off by Execute and either committed
(ExecContext::completeAcc) and, for stores, be sent to the store buffer.</p>

<p>Barrier instructions do not prevent cacheable loads from progressing to memory
but do cause a stream change which will discard that load. Stores will not be
committed to the store buffer if they are in the shadow of the barrier but
before the new instruction stream has arrived at Execute. As all other memory
transactions are delayed at the end of the requests queue until they are at the
head of Execute::inFlightInsts, they will be discarded by any barrier stream
change.</p>

<p>After commit, <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ_1_1BarrierDataRequest.html">LSQ::BarrierDataRequest</a>
requests are inserted into the store buffer to track each barrier until all
preceding memory transactions have drained from the store buffer. No further
memory transactions will be issued from the ends of FUs until after the barrier
has drained.</p>

<h4 id="draining">Draining</h4>

<p>Draining is mostly handled by the <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a> stage. When
initiated by calling <a href="https://gem5.github.io/gem5-doxygen/classMinorCPU.html#a3191c9247cd80dfc603bfcd154cf09a0">MinorCPU::drain</a>,
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Pipeline.html#af07fdce00c8937e9de5b6450a1cd62bf">Pipeline::evaluate</a>
checks the draining status of each unit each cycle and keeps the pipeline
active until draining is complete. It is Pipeline that signals the completion
of draining. Execute is triggered by <a href="https://gem5.github.io/gem5-doxygen/classMinorCPU.html#a3191c9247cd80dfc603bfcd154cf09a0">MinorCPU::drain</a>
and starts stepping through its <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40">Execute::DrainState</a>
state machine, starting from state Execute::NotDraining, in this order:</p>

<table>
  <tbody>
    <tr>
      <td>State</td>
      <td>Meaning</td>
    </tr>
    <tr>
      <td><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40aeecf47987ef0d4aa0a6a59403d085ec9">Execute::NotDraining</a></td>
      <td>Not trying to drain, normal execution</td>
    </tr>
    <tr>
      <td><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40aec53785380b6256e2baa889739311570">Execute::DrainCurrentInst</a></td>
      <td>Draining micro-ops to complete inst.</td>
    </tr>
    <tr>
      <td><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40a516d421a79c458d376bedeb067fc207f">Execute::DrainHaltFetch</a></td>
      <td>Halt fetching instructions</td>
    </tr>
    <tr>
      <td><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40ade3ca2567fed8d893896d71bb95f13ca">Execute::DrainAllInsts</a></td>
      <td>Discarding all instructions presented</td>
    </tr>
  </tbody>
</table>

<p>When complete, a drained Execute unit will be in the <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40ade3ca2567fed8d893896d71bb95f13ca">Execute::DrainAllInsts</a>
state where it will continue to discard instructions but has no knowledge of
the drained state of the rest of the model.</p>

<h2 id="debug-options">Debug options</h2>

<p>The model provides a number of debug flags which can be passed to gem5 with the
<code class="highlighter-rouge">–debug-flags</code> option.</p>

<p>The available flags are:</p>

<table>
  <thead>
    <tr>
      <th style="text-align: left">Debug flag</th>
      <th style="text-align: left">Unit which will generate debugging output</th>
    </tr>
  </thead>
  <tbody>
    <tr>
      <td style="text-align: left">Activity</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/namespaceDebug.html">Debug</a> ActivityMonitor actions</td>
    </tr>
    <tr>
      <td style="text-align: left">Branch</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html">Fetch2</a> and <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a> branch prediction decisions</td>
    </tr>
    <tr>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinorCPU.html">MinorCPU</a></td>
      <td style="text-align: left">CPU global actions such as wakeup/thread suspension</td>
    </tr>
    <tr>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html">Decode</a></td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html">Decode</a></td>
    </tr>
    <tr>
      <td style="text-align: left">MinorExec</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a> behaviour</td>
    </tr>
    <tr>
      <td style="text-align: left">Fetch</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a> and <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html">Fetch2</a></td>
    </tr>
    <tr>
      <td style="text-align: left">MinorInterrupt</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a> interrupt handling</td>
    </tr>
    <tr>
      <td style="text-align: left">MinorMem</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a> memory interactions</td>
    </tr>
    <tr>
      <td style="text-align: left">MinorScoreboard</td>
      <td style="text-align: left"><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a> scoreboard activity</td>
    </tr>
    <tr>
      <td style="text-align: left">MinorTrace</td>
      <td style="text-align: left">Generate MinorTrace cyclic state trace output (see below)</td>
    </tr>
    <tr>
      <td style="text-align: left">MinorTiming</td>
      <td style="text-align: left">MinorTiming instruction timing modification operations</td>
    </tr>
  </tbody>
</table>

<p>The group flag <a href="https://gem5.github.io/gem5-doxygen/namespaceMinor.html">Minor</a>
enables all the flags beginning with <a href="https://gem5.github.io/gem5-doxygen/namespaceMinor.html">Minor</a>.</p>

<h2 id="minortrace-and-minorviewpy">MinorTrace and minorview.py</h2>

<p>The debug flag MinorTrace causes cycle-by-cycle state data to be printed which
can then be processed and viewed by the minorview.py tool. This output is very
verbose and so it is recommended it only be used for small examples.</p>

<h3 id="minortrace-format">MinorTrace format</h3>

<p>There are three types of line outputted by MinorTrace:</p>

<h4 id="minortrace---ticked-unit-cycle-state">MinorTrace - Ticked unit cycle state</h4>

<p>For example:</p>

<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code> 110000: system.cpu.dcachePort: MinorTrace: state=MemoryRunning in_tlb_mem=0/0
</code></pre></div></div>

<p>For each time step, the MinorTrace flag will cause one MinorTrace line to be
printed for every named element in the model.</p>

<h4 id="minorinst---summaries-of-instructions-issued-by-decode">MinorInst - summaries of instructions issued by Decode</h4>

<p><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html">Decode</a></p>

<p>For example:</p>

<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code> 140000: system.cpu.execute: MinorInst: id=0/1.1/1/1.1 addr=0x5c \
                             inst="  mov r0, #0" class=IntAlu
</code></pre></div></div>

<p>MinorInst lines are currently only generated for instructions which are committed.</p>

<h4 id="minorline---summaries-of-line-fetches-issued-by-fetch1">MinorLine - summaries of line fetches issued by Fetch1</h4>

<p><a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a></p>

<p>For example:</p>

<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code>  92000: system.cpu.icachePort: MinorLine: id=0/1.1/1 size=36 \
                                vaddr=0x5c paddr=0x5c
</code></pre></div></div>

<h3 id="minorviewpy">minorview.py</h3>

<p>Minorview (util/minorview.py) can be used to visualise the data created by
MinorTrace.</p>

<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code>usage: minorview.py [-h] [--picture picture-file] [--prefix name]
                   [--start-time time] [--end-time time] [--mini-views]
                   event-file

Minor visualiser

positional arguments:
  event-file

optional arguments:
  -h, --help            show this help message and exit
  --picture picture-file
                        markup file containing blob information (default:
                        &lt;minorview-path&gt;/minor.pic)
  --prefix name         name prefix in trace for CPU to be visualised
                        (default: system.cpu)
  --start-time time     time of first event to load from file
  --end-time time       time of last event to load from file
  --mini-views          show tiny views of the next 10 time steps
</code></pre></div></div>

<p>Raw debugging output can be passed to minorview.py as the event-file. It will
pick out the MinorTrace lines and use other lines where units in the simulation
are named (such as system.cpu.dcachePort in the above example) will appear as
‘comments’ when units are clicked on the visualiser.</p>

<p>Clicking on a unit which contains instructions or lines will bring up a speech
bubble giving extra information derived from the MinorInst/MinorLine lines.</p>

<p><code class="highlighter-rouge">–start-time</code> and <code class="highlighter-rouge">–end-time</code> allow only sections of debug files to be loaded.</p>

<p><code class="highlighter-rouge">–prefix</code> allows the name prefix of the CPU to be inspected to be supplied.
This defaults to <code class="highlighter-rouge">system.cpu</code>.</p>

<p>In the visualiser, The buttons Start, End, Back, Forward, Play and Stop can be
used to control the displayed simulation time.</p>

<p>The diagonally striped coloured blocks are showing the <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1InstId.html">InstId</a> of the
instruction or line they represent. Note that lines in <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a> and f1ToF2.F
only show the id fields of a line and that instructions in <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html">Fetch2</a>, f2ToD, and
decode.inputBuffer do not yet have execute sequence numbers. The T/S.P/L/F.E
buttons can be used to toggle parts of <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1InstId.html">InstId</a> on and off to
make it easier to understand the display. Useful combinations are:</p>

<table>
  <thead>
    <tr>
      <th style="text-align: left">Combination</th>
      <th style="text-align: left">Reason</th>
    </tr>
  </thead>
  <tbody>
    <tr>
      <td style="text-align: left">E</td>
      <td style="text-align: left">just show the final execute sequence number</td>
    </tr>
    <tr>
      <td style="text-align: left">F/E</td>
      <td style="text-align: left">show the instruction-related numbers</td>
    </tr>
    <tr>
      <td style="text-align: left">S/P</td>
      <td style="text-align: left">show just the stream-related numbers (watch the stream sequence change with branches and not change with predicted branches)</td>
    </tr>
    <tr>
      <td style="text-align: left">S/E</td>
      <td style="text-align: left">show instructions and their stream</td>
    </tr>
  </tbody>
</table>

<p>The key to the right shows all the displayable colours (some of the colour
choices are quite bad!):</p>

<table>
  <thead>
    <tr>
      <th style="text-align: left">Symbol</th>
      <th style="text-align: left">Meaning</th>
    </tr>
  </thead>
  <tbody>
    <tr>
      <td style="text-align: left">U</td>
      <td style="text-align: left">Uknown data</td>
    </tr>
    <tr>
      <td style="text-align: left">B</td>
      <td style="text-align: left">Blocked stage</td>
    </tr>
    <tr>
      <td style="text-align: left">-</td>
      <td style="text-align: left">Bubble</td>
    </tr>
    <tr>
      <td style="text-align: left">E</td>
      <td style="text-align: left">Empty queue slot</td>
    </tr>
    <tr>
      <td style="text-align: left">R</td>
      <td style="text-align: left">Reserved queue slot</td>
    </tr>
    <tr>
      <td style="text-align: left">F</td>
      <td style="text-align: left">Fault</td>
    </tr>
    <tr>
      <td style="text-align: left">r</td>
      <td style="text-align: left">Read (used as the leftmost stripe on data in the dcachePort)</td>
    </tr>
    <tr>
      <td style="text-align: left">w</td>
      <td style="text-align: left">Write “ “</td>
    </tr>
    <tr>
      <td style="text-align: left">0 to 9</td>
      <td style="text-align: left">last decimal digit of the corresponding data</td>
    </tr>
  </tbody>
</table>

<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code>    ,---------------.         .--------------.  *U
    | |=|-&gt;|=|-&gt;|=| |         ||=|||-&gt;||-&gt;|| |  *-  &lt;- Fetch queues/LSQ
    `---------------'         `--------------'  *R
    === ======                                  *w  &lt;- Activity/Stage activity
                              ,--------------.  *1
    ,--.      ,.      ,.      | ============ |  *3  &lt;- Scoreboard
    |  |-\[]-\||-\[]-\||-\[]-\| ============ |  *5  &lt;- Execute::inFlightInsts
    |  | :[] :||-/[]-/||-/[]-/| -. --------  |  *7
    |  |-/[]-/||  ^   ||      |  | --------- |  *9
    |  |      ||  |   ||      |  | ------    |
[]-&gt;|  |    -&gt;||  |   ||      |  | ----      |
    |  |&lt;-[]&lt;-||&lt;-+-&lt;-||&lt;-[]&lt;-|  | ------    |-&gt;[] &lt;- Execute to Fetch1,
    '--`      `'  ^   `'      | -' ------    |        Fetch2 branch data
             ---. |  ---.     `--------------'
             ---' |  ---'       ^       ^
                  |   ^         |       `------------ Execute
  MinorBuffer ----' input       `-------------------- Execute input buffer
                    buffer
</code></pre></div></div>

<p>Stages show the colours of the instructions currently being
generated/processed.</p>

<p>Forward FIFOs between stages show the data being pushed into them at the
current tick (to the left), the data in transit, and the data available at
their outputs (to the right).</p>

<p>The backwards FIFO between <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html">Fetch2</a> and <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a> shows branch
prediction data.</p>

<p>In general, all displayed data is correct at the end of a cycle’s activity at
the time indicated but before the inter-stage FIFOs are ticked. Each FIFO has,
therefore an extra slot to show the asserted new input data, and all the data
currently within the FIFO.</p>

<p>Input buffers for each stage are shown below the corresponding stage and show
the contents of those buffers as horizontal strips. Strips marked as reserved
(cyan by default) are reserved to be filled by the previous stage. An input
buffer with all reserved or occupied slots will, therefore, block the previous
stage from generating output.</p>

<p>Fetch queues and <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ.html">LSQ</a> show the
lines/instructions in the queues of each interface and show the number of
lines/instructions in TLB and memory in the two striped colours of the top of
their frames.</p>

<p>Inside <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a>, the horizontal
bars represent the individual FU pipelines. The vertical bar to the left is the
input buffer and the bar to the right, the instructions committed this cycle.
The background of <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a> shows
instructions which are being committed this cycle in their original FU pipeline
positions.</p>

<p>The strip at the top of the <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a> block shows the
current streamSeqNum that <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a> is committing.
A similar stripe at the top of <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html">Fetch1</a> shows that
stage’s expected streamSeqNum and the stripe at the top of <a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html">Fetch2</a> shows its
issuing predictionSeqNum.</p>

<p>The scoreboard shows the number of instructions in flight which will commit a
result to the register in the position shown. The scoreboard contains slots for
each integer and floating point register.</p>

<p>The Execute::inFlightInsts queue shows all the instructions in flight in
<a href="https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html">Execute</a> with
the oldest instruction (the next instruction to be committed) to the right.</p>

<p><code class="highlighter-rouge">Stage activity</code> shows the signalled activity (as E/1) for each stage (with CPU
miscellaneous activity to the left)</p>

<p><code class="highlighter-rouge">Activity</code> show a count of stage and pipe activity.</p>

<h3 id="minorpic-format">minor.pic format</h3>

<p>The minor.pic file (src/minor/minor.pic) describes the layout of the models
blocks on the visualiser. Its format is described in the supplied minor.pic
file.</p>


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